1. Field
This disclosure relates generally to the layout of an integrated circuit, and more specifically, to the design of logic blocks in an integrated circuit.
2. Related Art
As semiconductor devices decrease in size, the effects of the variability in process performance increase. Therefore, there is a desire to make design layouts of the semiconductor devices more regular to decrease sensitivity to process variability. However, such methods undesirably increase the semiconductor device size. This increases area costs by decreasing the number the die that can be manufactured on the wafer. In addition, yield may be reduced because the area affected by a random defect is greater for larger devices.